1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to detecting and preventing the effects of a single event latch-up in an integrated circuit.
2. Discussion of Related Art
A latch-up occurs when an unintended path is created in an integrated circuit by triggering a parasitic device within the integrated circuit (“IC”). A parasitic device may be inadvertently formed in any location of the integrated circuit by placing two or more devices in close proximity. For example, a parasitic device or structure may occur when a PNPN structure is inadvertently formed, resulting in a silicon-controlled rectifier (SCR). FIG. 1A, for example, shows an integrated circuit with a PNP/NPN structure that may inadvertently result in a parasitic device with a PNPN structure. In FIG. 1A, each PN junction may have a diode drop voltage of 0.6 V.
A single event latch-up (SEL) may be caused in an IC by a number of triggering events, such as, for example, the IC being subjected to cosmic rays and experiencing spikes of voltage on an input or output terminal. A triggering event may create free carriers in the substrate or in the wells of the IC. If the area of the substrate subjected to the triggering event exceeds the area of other components, such as wells, subjected to the triggering event, then the number of majority carriers generated in the substrate may be higher than the number of carriers generated in the other components. Because the majority carriers created in the substrate by the triggering event may outnumber the carriers created in other devices, not all majority carriers in the substrate may re-combine, causing the majority carriers in the substrate to begin collecting in the substrate. As majority carriers collect in the substrate, the resulting current flow (I) in the substrate, which has a resistance r per unit distance, may create a voltage across the substrate from the junction to the substrate tap. If this voltage is greater than the diode drop voltage of the PN junctions, then an SCR may be inadvertently formed, possibly causing an SEL. FIG. 1B shows an example of the integrated circuit in FIG. 1A in which a PNPN junction has formed. Similar events may cause a parasitic device to form in a well on an IC.
The current flow caused by an SEL may damage the integrated circuit. For example, the excessive current caused by an SEL may flow through the created low-impedance path, possibly causing the circuit to be destroyed by the excessive current flow. Even if the SEL does not destroy the circuit, the device may have to be power-cycled to recover device functions. CMOS devices have inherent parasitic PNPN structures that are formed during fabrication of transistors in a semiconductor substrate. As technology trends towards developing smaller and higher performance integrated circuits, CMOS devices become more susceptible to SELs.
Testing for potential SEL sites is typically accomplished by scanning the circuit with neutron beams at an integrated repair operations center (IROC). At IROC, the circuit to be tested is placed under neutron beams and SELs are determined by counting the number of upsets that occur in the entire integrated circuit. The testing, however, can only indicate whether an SEL has occurred; it cannot detect where the SEL occurs in the integrated circuit unless the circuit is simultaneously functionally tested under the neutron beam using a test program. In addition to these drawbacks, the operator needs to know the layout of the circuit in order to determine the origin of the SEL. Moreover, the testing at IROC is costly and time consuming, and may require waiting for a period in which the facility is available for such testing (about twice a year); preparing the boards, hardware, and programming for testing at IROC may also require significant time.